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ai01184 13 a0-a12 w dq0-dq7 v cc m48z09 m48z19 g e2 v ss 8 e1 int figure 1. logic diagram m48z09 m48z19 cmos 8k x 8 zeropower sram integrated ultra low power sram, power-fail control circuit and battery unlimited write cycles read cycle time equals write cycle time automatic power-fail chip deselect and write protection power-fail interrupt choice of two write protect voltages: C m48z09: 4.5v v pfd 4.75v C m48z19: 4.2v v pfd 4.5v self contained battery in the caphat dip package 11 years of data retention in the absence of power pin and function compatible with the mk48z09, 19 and jedec standard 8k x 8 srams description the m48z09,19 zeropower ? ram is an 8k x 8 non-volatile static ram which is pin and function compatible with the mk48z09,19. a special 28 pin 600mil dip caphat ? package houses the m48z09,19 silicon with a long life lith- ium button cell to form a highly integrated battery backed-up memory solution. a0-a12 address inputs dq0-dq7 data inputs / outputs int power fail interrupt e1 chip enable 1 e2 chip enable 2 g output enable w write enable v cc supply voltage v ss ground table 1. signal names 28 1 pcdip28 (pc) battery caphat november 1994 1/13 obsolete product(s) - obsolete product(s)
symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off) C40 to 85 c v io input or output voltages C0.3 to 7 v v cc supply voltage C0.3 to 7 v i o output current 20 ma p d power dissipation 1 w note: stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the dev ice at these or any other conditions above those indicated in the op erational section of this specification is not implied. exposure to the absolute maximum ratings conditions for ext ended periods of t ime may affect reliability. caution: negat ive undershoots below C0.3 volts are not allowed on any pin while in the battery back-up mode. table 2. absolute maximum ratings mode v cc e1 e2 g w dq0-dq7 power deselect 4.75v to 5.5v or 4.5v to 5.5v v ih x x x high z standby deselect x v il x x high z standby write v il v ih xv il d in active read v il v ih v il v ih d out active read v il v ih v ih v ih high z active deselect v so to v pfd (min) x x x x high z cmos standby deselect v so x x x x high z battery back-up mode note : x = v ih or v il table 3. operating modes a1 a0 dq0 a7 a4 a3 a2 a6 a5 e2 a10 a8 a9 dq7 w a11 g e1 dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 int v cc ai01185 m48z09 m49z19 8 1 2 3 4 5 6 7 9 10 11 12 13 14 16 15 28 27 26 25 24 23 22 21 20 19 18 17 figure 2a. dip pin conn ections the m48z09,19 button cell has sufficient capacity and storage life to maintain data for an accumu- lated time period of at least 11 years in the absence of power over the operating temperature range. the m48z09,19 is a non-volatile pin and function equivalent to any jedec standard 8k x 8 sram. it also easily fits into many rom, eprom, and eeprom sockets, providing the non-volatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. the m48z09,19 also has its own power-fail detect circuit. the control circuitry constantly monitors the single 5v supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable system opera- tion brought on by low v cc . as v cc falls below approximately 3v, the control circuitry connects the battery which maintains data and clock operation until valid power returns. description (contd) 2/13 m48z09, m48z19 obsolete product(s) - obsolete product(s)
ai01398 5v out c l = 100pf or 30pf c l includes jig capacitance 1.8k w device under test 1k w figure 4. ac testing load circuit input rise and fall times 5ns input pulse voltages 0 to 3v input and output timing ref. voltages 1.5v ac measurement condi tions note that output hi-z is defined as the point where data is no longer driven. ai01397 lithium cell v pfd v cc v ss voltage sense and switching circuitry 8k x 8 sram array a0-a12 dq0-dq7 e1 w g power e2 int figure 3. block diagram read mode the m48z09,19 is in the read mode whenever w (write enable) is high, e1 (chip enable 1) is low, and e2 (chip enable 2) is high. the device archi- tecture allows ripple- through access of data from eight of 65,536 locations in the static storage array. thus, the unique address specified by the 13 ad- dress inputs defines which one of the 8,192 bytes of data is to be accessed. valid data will be avail- able at the data i/o pins within t avqv (address access time) after the last address input signal is stable, providing that the e1, e2, and g access times are also satisfied. if the e1, e2 and g access times are not met, valid data will be available after the latter of the chip enable access times (t e1lqv or t e2hqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e1, e2 and g. if the outputs are activated before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address inputs are changed while e1, e2 and g remain active, output data will remain valid for t axqx (out- put data hold time) but will go indeterminate until the next address access. 3/13 m48z09, m48z19 obsolete product(s) - obsolete product(s)
symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc 5 m a i cc supply current outputs open 80 ma i cc1 supply current (standby) ttl e1 = v ih , e2 = v il 3ma i cc2 supply current (standby) cmos e1 = v cc C 0.2v, e2 = v ss + 0.2v 3ma v il input low voltage C0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 v output low voltage ( int) (1) i ol = 0.5ma 0.4 v v oh output high voltage i oh = C1ma 2.4 v note: 1. the int pin is open drain. table 5. dc characteristics (t a = 0 to 70 c; v cc = 4.75v to 5.5v or 4.5v to 5.5v) symbol parameter test condition min max unit c in input capacitance v in = 0v 10 pf c io (2) input / output capacitance v out = 0v 10 pf notes: 1. effective capacitance calculated from the equation c = i d t/ d v with d v = 3v and p ower supply at 5v. 2. outputs deselected table 4. capacitance (1) (t a = 25 c) symbol parameter min typ max unit v pfd power-fail deselect voltage (m48z09) 4.5 4.6 4.75 v v pfd power-fail deselect voltage (m48z19) 4.2 4.3 4.5 v v so battery back-up switchover voltage 3.0 v t dr expected data retention time 11 years note: 1. all voltages referenced to v ss . table 6. power down/up trip points dc characteristics (1) (t a = 0 to 70 c) 4/13 m48z09, m48z19 obsolete product(s) - obsolete product(s)
symbol parameter min max unit t pd e1 or w at v ih or e2 at v il before power down 0 m s t f (1) v pfd (max) to v pfd (min) v cc fall time 300 m s t fb (2) v pfd (min) to v so v cc fall time 10 m s t r v pfd (min) to v pfd (max) v cc rise time 0 m s t rb v so to v pfd (min) v cc rise time 1 m s t rec e1 or w at v ih or e2 at v il after power up 1 ms t pfx int low to auto deselect 10 40 m s t pfh (3) v pfd (max) to int high 120 m s notes :1.v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occur ring until 200 m s after v cc passes v pfd (min). 2. v pfd (min) to v so fall time of less than t fb may cause corruption of ram data. 3. int may go high anytime after v cc exceeds v pfd (min) and is guaranteed to go high t pfh after v cc exceeds v pfd (max). table 7. power down/up mode ac characteristics (t a = 0 to 70 c) ai00566 v cc inputs int (per control input) outputs don't care high-z tf tfb tpfx tr tpfh trec tpd trb tdr valid valid note (per control input) recognized recognized v pfd (max) v pfd (min) v so figure 5. power down/up mode ac w aveforms note: inputs may or may not be recognized at this time. caution should be taken to keep e1 high or e2 low as v cc rises past v pfd (min). some systems may performs inadvertent write cycles after v cc rises above v pfd (min) but before normal system operations begins. even though a power on reset is being applied to the pr ocessor a reset condition may not occur until after the system clock is r unning. 5/13 m48z09, m48z19 obsolete product(s) - obsolete product(s)
symbol parameter m48z09 / 19 unit -100 min max t avav read cycle time 100 ns t avqv (1) address valid to output valid 100 ns t e1lqv (1) chip enable 1 low to output valid 100 ns t e2hqv (1) chip enable 2 high to output valid 100 ns t glqv (1) output enable low to output valid 50 ns t e1lqx (2) chip enable 1 low to output transition 10 ns t e2hqx (2) chip enable 2 high to output transition 10 ns t glqx (2) output enable low to output transition 5 ns t e1hqz (2) chip enable 1 high to output hi-z 50 ns t e2lqz (2) chip enable 2 low to output hi-z 50 ns t ghqz (2) output enable high to output hi-z 40 ns t axqx (1) address transition to output transition 5 ns notes: 1. c l = 100pf (see figure 4). 2. c l = 30pf (see figure 4) table 8. read mode ac characteristics (t a = 0 to 70 c; v cc = 4.75v to 5.5v or 4.5v to 5.5v) ai00962 tavav tavqv taxqx te1lqv te1lqx te1hqz tglqv tglqx tghqz valid a0-a12 e1 g dq0-dq7 te2hqv te2hqx valid te2lqz e2 figure 6. read mode ac w aveforms 6/13 m48z09, m48z19 obsolete product(s) - obsolete product(s)
symbol parameter m48z09 / 19 unit -100 min max t avav write cycle time 100 ns t avwl address valid to write enable low 0 ns t ave1l address valid to chip enable 1 low 0 ns t ave2h address valid to chip enable 2 high 0 ns t wlwh write enable pulse width 80 ns t e1le1h chip enable 1 low to chip enable 1 high 80 ns t e2he2l chip enable 2 high to chip enable 2 low 80 ns t whax write enable high to address transition 10 ns t e1hax chip enable 1 high to address transition 10 ns t e2lax chip enable 2 low to address transition 10 ns t dvwh input valid to write enable high 50 ns t dve1h input valid to chip enable 1 high 50 ns t dve2l input valid to chip enable 2 low 50 ns t whdx write enable high to input transition 5 ns t e1hdx chip enable 1 high to input transition 5 ns t e2ldx chip enable 2 low to input transition 5 ns t wlqz (1, 2) write enable low to output hi-z 50 ns t avwh address valid to write enable high 80 ns t ave1h address valid to chip enable 1 high 80 ns t ave2l address valid to chip enable 2 low 80 ns t whqx (1, 2) write enable high to output transition 10 ns notes: 1. c l = 30pf (see figure 4). 2. if e1 goes low or e2 high simultaneously with w going low, the outputs remain in the high impedance state. table 9. write mode ac characteristics (t a = 0 to 70 c; v cc = 4.75v to 5.5v or 4.5v to 5.5v) 7/13 m48z09, m48z19 obsolete product(s) - obsolete product(s)
ai00963 tavav twhax tdvwh data input a0-a12 e1 w dq0-dq7 valid e2 tavwh tave1l tave2h twlwh tavwl twlqz twhdx twhqx figure 7. write enable controlled, write ac waveforms ai00964b tavav te1hax tdve1h tdve2l a0-a12 e1 w dq0-dq7 valid e2 tave1h tave1l tavwl tave2l te1le1h te2lax tave2h te2he2l te1hdx te2ldx data input figure 8. chip enable controlled, write ac waveforms 8/13 m48z09, m48z19 obsolete product(s) - obsolete product(s)
write mode the m48z09,19 is in the write mode whenever w, e1, and e2 are active. the start of a write is refer- enced from the latter occurring falling edge of w or e1, or the rising edge of e2. a write is terminated by the earlier rising edge of w or e1, or the falling edge of e2. the addresses must be held v alid throughout the cycle. e1 or w must return high or e2 low for minimum of t e1hax or t e2lax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data-in must be valid t dvwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e1 and g and a high on e2, a low on w will disable the outputs t wlqz after w falls. data retention mode with valid v cc applied, the m48z09,19 operates as a conventional bytewide ? static ram. should the supply voltage decay, the ram will automat- ically power-fail deselect, write protecting itself when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high impedance, and all inputs are treated as "dont care." note: a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the rams content. at voltages below v pfd (min), the user can be as- sured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the m48z09,19 may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . therefore, decoupling of the power supply lines is recom- mended. when v cc drops below v so , the control circuit switches power to the internal battery which pre- serves data and powers the clock. the internal button cell will maintain data in the m48z09,19 for an accumulated period of at least 10 years when v cc is less than v so . as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . write protection continues until v cc reaches v pfd (min). e1 should be kept high or e2 low as v cc rises past v pfd (min) to prevent inadvertent write cycles prior to processor stabilization. normal ram operation can resume t rec after v cc exceeds v pfd (max). power fail interrupt pin the m48z09,19 continuously monitors v cc . when v cc falls to the power-fail detect trip point, an interrupt is immediately generated. an internal clock provides a delay of between 10 m s and 40 m s before automatically deselecting the m48z09,19. the int pin is an open drain output and requires an external pull up resistor, even if the interrupt output function is not being used. system battery life the useful life of the battery in the m48z09,19 is expected to ultimately come to an end for one of two reasons: either because it has been discharged while providing current to the ram in the battery back-up mode, or because the effects of aging render the cell useless before it can actually be completely discharged. the two effects are virtually unrelated allowing dischar ge, or capacity con- sumption, and the effects of aging, or storage life, to be treated as two independent but simultaneous mechanisms. the earlier occurring failure mecha- nism defines the battery system life of the m48z09,19. cell storage life storage life is primarily a function of temperature. figure 9 illustrates the approximate storage life of the m48z09,19 battery over temperature. the re- sults in figure 9 are derived from temperature accelerated life test studies performed at sgs- thomson. for the purpose of the testing, a cell failure is defined as the inability of a cell stabilized at 25 c to produce a 2.4v closed circuit voltage across a 250 k w load resistor. the two lines, t 1% and t 50% , represent different failure rate distribu- tions for the cells storage life. at 70 c, for example, the t 1% line indicates that an m48z09,19 has a 1% chance of having a battery failure 28 years into its life while the t 50% shows the part has a 50% chance of failure at the 50 year mark. the t 1% line repre- sents the practical onset of wear out and can be considered the worst case storage life for the cell. the t 50% can be considered the normal or average life. 9/13 m48z09, m48z19 obsolete product(s) - obsolete product(s)
calculating storage life the following formula can be used to predict stor- age life: 1 {[(ta1/tt)/sl1]+[(ta2/tt)/sl2]+...+[(tan/tt)/sln]} where, C ta1, ta2, tan = time at ambient temperature 1, 2, etc. C tt = total time = ta1+ta2+ ...+tan C sl1, sl2, sln = storage life at temperature 1, 2, etc. for example an m48z09,19 is exposed to tempera- tures of 55 c or less for 8322 hrs/yr, and tempera- tures greater than 60 c but less than 70 c for the remaining 438 hrs/yr. reading predicted t 1% values from figure 9, C sl1 @ 200 yrs, sl2 = 28 yrs C tt = 8760 hrs/yr C ta1 = 8322 hrs/yr, ta2 = 438 hrs/yr predicted storage life 3 1 {[(8322/8760)/200]+[(431/8760)/28]} or 154 years. as can be seen from these calculations and the results, the expected life time of the m48z09, 19 should exceed most system requirements. estimated system life since either storage life or capacity consumption can end the batterys life, the system life is marked by which ever occurs first. reference for system life each m48z09,19 is marked with a nine digit manu- facturing date code in the form of h99xxyyzz. for example, h995b9431 is: h = fabricated in carrollton, tx 9 = assembled in muar, malaysia, 9 = tested in muar, malaysia, 5b = lot designator, 9431 = assembled in the year 1994, work week 31. ai01399 20 30 40 50 60 70 80 90 1 2 3 4 5 8 6 temperature (degrees celsius) 10 20 30 40 50 years t50% (average) t1% figure 9. predicted battery storage life versus temperature 10/13 m48z09, m48z19 obsolete product(s) - obsolete product(s)
ordering information scheme supply voltage and write protect voltage 09 v cc = 4.75v to 5.5v v pfd = 4.5v to 4.75v 19 v cc = 4.5v to 5.5v v pfd = 4.2v to 4.5v speed -100 100ns package pc pcdip28 temp. range 1 0 to 70 c example: m48z09 -100 pc 1 for a list of available options (supply voltage, speed, package, etc...) refer to the current memory shortform catalogue. for further information on any aspect of this device, please contact the sgs-thomson sales office nearest to you. 11/13 m48z09, m48z19 obsolete product(s) - obsolete product(s)
pcdip a2 a1 a l b1 b e1 d e n 1 c ea e3 symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.38 8.89 0.330 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 39.37 39.88 1.550 1.570 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 29.72 36.32 1.170 1.430 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n28 28 pcdip28 draw ing is not to scale pcdip28 - 28 pin plastic dip, battery caphat 12/13 m48z09, m48z19 obsolete product(s) - obsolete product(s)
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third part ies which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelec tronics. specifications mentioned in this publication are subject to change without notice. this publi cation supersedes and replaces all information previously s upplied. sgs-thomson microelectronics products are not authorized for use as critical comp onents in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved ? zeropower is a registered trademark of sgs-thomson microelectronics ? caphat and bytewide are trademarks of sgs-thomson microelectronics sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - i taly - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - t aiwan - thailand - united kingdom - u.s.a. 13/13 m48z09, m48z19 obsolete product(s) - obsolete product(s)

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